1. Field of the Invention
The present invention relates generally to the field of electrical devices. More particularly, the present invention relates to the field of digital logic gates.
2. Description of the Related Art
Complementary Metal Oxide Semiconductor (CMOS) circuits are well known in the Integrated Circuit (IC) industry and typically include many CMOS stages configured together in a digital logic path. A typical CMOS stage includes a pull-up path and a pull-down path coupled in series between a high voltage source and a low voltage source. The pull-up path drives the output of the stage to the high voltage source to output a high or logical-one signal. The pull-down path drives the output of the stage to the low voltage source to output a low or logical-zero signal. As one example, the high and low voltage source levels may be approximately 3.3 Volts and approximately zero (0) Volts, respectively.
A typical CMOS stage switches its output from low to high by turning on the pull-up path while simultaneously turning off the pull-down path. Similarly, a typical CMOS stage switches its output from high to low by turning on the pull-down path while simultaneously turning off the pull-up path. Both paths, however, are partially on simultaneously for a finite amount of time while transitioning between on and off states, allowing current to flow between the high voltage source and the low voltage source.
This flow of current, commonly called overlap or crowbar current, represents wasted current that performs no useful work and results in increased power consumption for the stage. Overlap current may consume ten percent or more of the current consumed by the stage, reducing the amount of current available for the stage to drive its output. With less current available, the stage undergoes an increased delay in switching its output from low to high and from high to low.
Furthermore, both the pull-up path and the pull-down path for a typical CMOS stage are coupled to the input of the stage and present a load to any preceding CMOS stage even though only one of the paths is actually driving the stage output. This increased loading results in an increased delay for any preceding stage in switching its output from low to high and from high to low.
The fanout of stages, that is the ratio of the channel width size of the driven device or devices to the channel width size of the driving device or devices, may be appropriately adjusted to reduce the delay that results from such increased loading. However, any increase in size for driving and/or driven devices to reduce this delay may result in increased current consumption. Any increase in device size may also require relatively more layout area.
Self-resetting logic circuits may provide for relatively faster switching times and relatively less current consumption as compared to typical CMOS circuits.
U.S. Pat. No. 4,985,643 by Proebsting, entitled SPEED ENHANCEMENT TECHNIQUE FOR CMOS CIRCUITS, disclosed one self-resetting logic circuit. In a series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from subsequent logic stages. The width of the pulse propagating from stage to stage in the signal path remains substantially constant.
For the self-resetting logic circuit of Proebsting, however, the feedback delay for each stage must be nearly identical to avoid overlap current and realize a speed increase over typical CMOS circuits. As the propagation delay of any inverter gate in the feedback path varies depending on such factors as the proximity of each inverter gate to any previous inverter gate, any differences in the power supply voltage for each inverter gate, and any noise in the power supply, ensuring nearly identical feedback delay for each stage may be difficult. When an overlap current condition occurs for one stage, overlap current results for subsequent stages as any timing problem encountered in one stage is propagated to the next stage. A domino effect may result as successive stages undergo similar or worse timing problems, causing the circuit to fail from excessive power consumption.